1. Field of the Invention
The invention relates to microprocessors and, more particularly, to a method for erasing a semiconductor memory associated with a microprocessor as well as to the circuits for the implementation thereof.
This memory is of the electrically erasable and programmable read-only type, better known as a FLASH EEPROM type. Such a memory is designed for recording instructions of the programs that are used by the central processing unit of the microprocessor to carry out the sequence of operations on the information or data elements to be processed. As a result of this use, this memory is addressed usually for the reading therein of the information elements that it contains, with the recording of the information elements being done from time to time in order to change the instructions therein as a function of the programs to be implemented. This recording is preceded by an operation for the erasure of the memory in order to place all its memory cells in a determined binary state.
2. Discussion of the Related Art
Such semiconductor memories have increasingly greater capacities that may possibly go up to 16-64 million memory cells (16 to 64 megabits) and are designed to replace magnetic memories on rotary disks. These memories have the following main advantages:
short access time for reading, PA1 no rotating mechanical parts, PA1 low supply voltage, PA1 low electrical consumption, PA1 increased reliability, and PA1 their manufacture is integrated with that of the microprocessor. PA1 (A) erasing the memory by the simultaneous application of a pulse to all the sectors; PA1 (B) checking, sector by sector, the erasure of each cell of the memory; PA1 (C) locking each sector for which the checking has not detected any unerased cell; PA1 (D) checking that all the sectors are locked, if the answer is positive, the erasing operation ends, if the answer is negative, it proceeds to the next step; PA1 (E) applying an erasure pulse to the unlocked sectors; PA1 (F) checking, sector after sector, the unlocked sectors; PA1 (G) returning to the step (C). PA1 a gate circuit on the supply circuit for the erasure of a sector to which the erasure pulse is applied; and PA1 a logic circuit for activating the closing or opening of the gate circuit depending on whether or not the sector is locked so that the sector is again erased only if said sector has at least one unerased cell.
In order to modify the information elements in these semiconductor memories, it is necessary, as indicated hereabove, to erase them in order to place all the memory cells in a determined binary state, namely 1 or 0.
This erasing operation consists not only in erasing the memory cells but also in subsequently ascertaining that the erasure has indeed resulted in the determined binary state. If the verification indicates that certain memory cells are not in the desired state, a second erasing operation is performed, followed by a second checking operation, and so forth. This may result in a very lengthy period of erasure, on the order of several seconds, for there may be several hundreds of erasure cycles. Furthermore, when the erasure cycles occur, a phenomenon of cell depletion occurs and the conduction threshold of the cells is lowered.
The present invention is aimed at implementing a method for the total erasure of a semiconductor memory that leads to a reduction of the total duration of the erasure operation.
Semiconductor memories of this type, for example 64-megabit memories, may be organized in 32 sectors, each having 512,000 memory cells. This enables the recording, in each sector, of 64,000 words having eight bits each.
In the standard type of erasing method, the erasure is done sector by sector and consists in applying an erasure pulse to a selected sector, then ascertaining that each cell of the selected sector has been erased and applying another erasure pulse to the selected sector as soon as a faulty cell has been detected. This procedure leads to an erasure time that may be lengthy.
The method of the invention consists in applying an erasure pulse simultaneously to all the sectors, then in verifying the erasure sector after sector, locking the sector for which the verification has been satisfactory, applying a new erasure pulse to the unlocked sectors and then checking these unlocked sectors. Thus, the successive erasure cycles are applied only to sectors having defects of erasure. In this way, the erasure is checked only for sectors for which the previous verification had revealed defects. This leads to an appreciable gain in time. Furthermore, the erasure itself relates only to sectors having erasure defects. This reduces the phenomenon of depletion of the cells.